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| OKI Semiconductor ML9371 64-Channel Organic EL Cathode Driver PEDL9371-01 Issue Date: Dec. 9, 2002 Preliminary GENERAL DESCRIPTION The ML9371 is an organic EL cathode driver LSI with 64 outputs. Since this LSI has the output condition setting function, which allows setting of all outputs High, all outputs Low, and all outputs High Impedance, the user can set driving methods suited to the characteristics of individual organic EL panel. When combined with ML9361 the organic EL anode driver, the ML9371 can drive a 64 x 128 full-dot panel. FEATURES * * * * * * * * * Logic power supply voltage : 3.0 to 5.5 V EL drive voltage : 8.0 to 30 V Cathode outputs : 64 outputs Cathode low output current : 150 mA (max.) Cathode high output current : -50 mA (max.) Cathode low ON-resistance : 5 (max.) Cathode high ON-resistance : 100 (max.) All outputs High, all outputs Low, all outputs High Impedance Package : Gold bump chip (TCP is tailored for each customer requirement) 1/11 PEDL9371-01 OKI Semiconductor ML9371 BLOCK DIAGRAM OUT1 OUT64 VDISP D-GND Cathode driver VDD HZ ALL H ALL L TEST RES PO1 DATA I/O CLK I/O F/R L-GND SIO CIO F/R RES Output control circuit PO64 Shift register SOI COI DATA O/I CLK O/I PIN CONFIGURATION (View from the Pad Layout Side) OUT1 OUT2 D-GND D-GND VDISP VDISP DATA I/O ALL H ALL L HZ TEST OUT63 OUT64 D-GND D-GND VDISP VDISP F/R VDD CLK O/I L-GND DATA O/I ML9371 RES CLK I/O 2/11 PEDL9371-01 OKI Semiconductor ML9371 PIN DESCRIPTION Symbol VDISP VDD D-GND L-GND Type Description VDISP is the cathode driver circuit power supply pin. VDD is the logic circuit power supply pin. D-GND is a ground pin for cathode driver circuit. L-GND is a ground pin for logic circuit. D-GND and L-GND should be connected outside the LSI. Input pin for register initialization signal. When this pin is set low, the LSI enters the following initial setting states: * Shift register outputs (POm): all "low" (m = 1 to 64) * All cathode drive signal outputs (OUT1 to OUT64): "high impedance" Input pin for data transfer direction select signal for shift register. * When this pin is low, data is transferred starting at PO1 toward PO64. * When this pin is high, data is transferred starting at PO64 toward PO1. Cathode scan data input-output pin. When the F/R pin is low, this pin is an input pin, and when it is high, this pin is an output pin. Cathode scan data input-output pin. When the F/R pin is low, this pin is an output pin, and when it is high, this pin is an input pin. Cathode scan data transfer clock input-output pin. When the F/R pin is low, this pin is an input pin, and when it is high, this pin is an output pin. Cathode scan data transfer clock input-output pin. When the F/R pin is low, this pin is an output pin, and when it is high, this pin is an input pin. Input pin for cathode drive signal output control signal. When this pin is low, all cathode drive signal outputs (OUT1 to OUT64) are high impedance. Input pin for cathode drive signal output control signal. When this pin is high, all cathode drive signal outputs (OUT1 to OUT64) are high. Input pin for cathode drive signal output control signal. When this pin is high, all cathode drive signal outputs (OUT1 to OUT64) are low. Pin for production tests. Leave this pin open or connect it to L-GND. Cathode drive signal output pin. -- RES I F/R I DATA I/O I/O DATA O/I I/O CLK I/O I/O CLK O/I I/O HZ I ALL H ALL L TEST OUT 1 to 64 I I -- O 3/11 PEDL9371-01 OKI Semiconductor ML9371 FUNCTION TABLE 1. Shift Register Operation during Cathode Scan Data Transfer Input/Output DATA I/O Input Output Output CLK I/O Input L L H L H L H Output Output H L H PO1n to PO64n: States of PO1 to PO64 immediately before the clock rises PO 2n PO 2n PO 3n PO 3n RES L F/R L H CLK O/I Output Input DATA O/I Output Input PO 1 L L L Shift Register Parallel Out PO PO 2 63 L L L L PO 1n PO 1n PO 62n PO 62n PO 64 L L PO 63n PO 63n Output Output H Invariable PO 64n PO 64n H L H Invariable 2. Operation of Output Section RES L HZ X L ALL H X X H H H ALL L X X X H L L POm L X X X H L X: Don't Care OUTm High impedance High impedance High Low Low High 4/11 PEDL9371-01 OKI Semiconductor ML9371 OUTPUT WAVEFORMS When F/R is low RES HZ ALL H ALL L DATA I/O Input DATA O/I Output CLK I/O Input CLK O/I Output OUT 1 OUT 2 OUT 3 H.Z. H.Z. H.Z. OUT 63 OUT 64 H.Z. H.Z. 5/11 PEDL9371-01 OKI Semiconductor ML9371 ABSOLUTE MAXIMUM RATINGS Parameter Logic power supply voltage EL drive power supply voltage (cathode) Logic input voltage Logic output voltage EL driver output voltage EL driver output voltage (pulse)*1 EL driver output current Storage temperature *1 Consult Oki for customization of pulse width. Symbol VDD VDISP VIN VOUT VOUT-EL VOUT-ELP IELL (sink) IELH (source) Tstg Condition Ta = 25C Ta = 25C Ta = 25C Ta = 25C Applied to OUT1 to OUT64 Applied to OUT1 to OUT64 Applied to OUT1 to OUT64 -- Rating -0.3 to +6.5 -0.3 to +35 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -0.3 to VDISP + 0.3 -VDISP to 2 x VDISP 200 -70 -40 to +125 Unit V V V V V V mA mA C RECOMMENDED OPERATING CONDITIONS Parameter Logic power supply voltage EL drive power supply voltage (cathode) Logic input voltage EL driver output current Junction operating temperature Symbol VDD VDISP VIN IELL (sink) IELH (source) Tjop Applied to OUT1 to OUT64 Condition -- -- -- VO = 0.75 V VDISP = 14 V VO = VDISP - 5 V -- Range 3.0 to 5.5 8 to 30 0.0 to VDD 150 -50 -40 to +125 Unit V V V mA mA C 6/11 PEDL9371-01 OKI Semiconductor ML9371 ELECTRICAL CHARACTERISTICS DC Characteristics Parameter "H" input voltage "L" input voltage Schmitt voltage width Symbol VIH VIL VSH IIH1 "H" input current IIH2 IIL1 "L" input current IIL2 "H" output voltage "L" output voltage "H" output current "L" output current 1 "L" output current 2 VOH VOL IELH IELL1 IELL2 Applicable Pins All input pins All input pins CLK I/O, CLK O/I ALL H, ALL L DATA I/O, DATA O/I CLK I/O, CLK O/I Input state RES, F/R, HZ ALL H, ALL L DATA I/O, DATA O/I CLK I/O, CLK O/I Input state RES, F/R, HZ ALL H, ALL L DATA I/O, DATA O/I CLK I/O, CLK O/I Output state DATA I/O, DATA O/I CLK I/O, CLK O/I Output state OUT1 to OUT64 OUT1 to OUT64 OUT1 to OUT64 VDD = 3.0 to 5.5 V, VDISP = 8 to 30 V, Tjop = -40 to +125C Condition Min. Typ. Max. Unit -- 0.8VDD -- VDD V -- 0 -- 0.2VDD V VDD = 5.0 V VDD = 5.5 V VI = 5.5 V VDD = 5.5 V VI = 5.5 V VDD = 5.5 V VI = 0.0 V VDD = 5.5 V VI = 0.0 V VDD = 3.0 V IO = -200 A VDD = 3.0 V IO = 200 A VDISP = 14 V VO = 9 V Only one output is high VDISP = 14 V VO = 0.75 V Only one output is low VDISP = 14 V VO = 5 V ALL L = high VDD = 5.5 V, VDISP = 30 V Clock = 100 kHz The low state of only one *1 output is scanned. No load VDD = 5.5 V, VDISP = 30 V Clock = 10 kHz The low state of only *1 one output is scanned. No load VDD = 5.5 V, VDISP = 30 V Clock stopped RES = low No load VDD = 5.5 V, VDISP = 30 V Clock = 100 kHz The low state of only *1 one output is scanned. No load RES = low No load 0.4 -10 30 -10 -10 0.8VDD -- -50 150 50 -- -- -- -- -- -- -- -- -- -- 0.9 10 140 10 10 -- 0.2VDD -- -- -- V A A A A V V mA mA mA IDISP1 VDISP -- -- 30 mA IDISP2 VDISP -- -- 3 mA Supply current IDISPS VDISP -- -- 30 A IDD VDD -- -- 3 mA IDDS VDD -- -- 10 A *1 See the section of "OUTPUT WAVEFORMS". 7/11 PEDL9371-01 OKI Semiconductor ML9371 AC Characteristics VDD = 3.0 to 5.5 V, VDISP = 8 to 30 V, Tjop = -40 to +125C Parameter CLK frequency CLK pulse width DATA CLK setup time CLK DATA hold time Reset execution time RES CLK reset recovery time CLK input/output delay time Data output delay time Cathode output delay time Input signal rise/fall time Symbol fCLK tCW tDS tDH tRSON tRS tDCLK tDDATA tDr tDf tr tf Applicable pins CLK I/O, CLK O/I CLK I/O, CLK O/I CLK I/O, DATA I/O CLK O/I, DATA O/I CLK I/O, DATA I/O CLK O/I, DATA O/I VDD, RES CLK I/O, CLK O/I RES CLK I/O, CLK O/I CLK I/O, DATA O/I CLK O/I, DATA I/O RES, HZ, ALL H, ALL L OUT1 to OUT64 All input pins Condition -- -- -- -- -- -- CL = 45 pF CL = 45 pF Min. -- 5 50 50 250 250 -- -- Typ. -- -- -- -- -- -- -- -- Max. 100 -- -- -- -- -- 100 100 Unit kHz s ns ns ns ns ns ns s CL = 45 pF -- -- 2.0 -- -- -- 500 ns 8/11 PEDL9371-01 OKI Semiconductor ML9371 TIMING DIAGRAMS Data Input 0.9VDD tRSON VIL tRS VIH VIL tDS tDH 1/fCLK tCW VDD RES CLK I/O CLK O/I DATA I/O DATA O/I tCW VIH VIL tf 0.9VDD 0.1VDD tr All inputs Output Delay CLK I/O CLK O/I Input DATA I/O DATA O/I Output CLK I/O CLK O/I Input CLK O/I CLK I/O Output VIH tDCLK VOH VIL tDCLK VOL VIL tDDATA VIL tDDATA VOH VOL RES, HZ, ALL H, ALL L OUT1 to 64 VIH tDr/tDf 0.9VDISP VIL tDr/tDf 0.1VDISP POWER APPLYING SEQUENCE When applying power, apply it to the logic power supply (VDD) first, then to the EL drive power supply (VDISP). When turning the power off, turn off the EL drive power supply (VDISP) first, then the logic power supply (VDD). Make the RES pin high at least 250 ns after applying power to VDD. (Refer to Reset execution time in AC Characteristics.) 9/11 PEDL9371-01 OKI Semiconductor ML9371 REVISION HISTORY Document No. PEDL9371-01 Date Dec. 9, 2002 Page Previous Current Edition Edition - - Description Preliminary edition 1 10/11 PEDL9371-01 OKI Semiconductor ML9371 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2002 Oki Electric Industry Co., Ltd. 3. 4. 5. 6. 7. 8. 11/11 |
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